1. Field of the Invention
This invention relates to an etchant for etching silicon dioxide while not attacking silicon. In particular, the etchant etches the silicon dioxide while not substantially attacking N type, exposed silicon underlying the oxide and a metallic silicide.
2. Description of the Prior Art
In fabricating semiconductor devices it is the practice to passivate and protect the surface of a body of silicon material with a layer or superimposed layers of inorganic insulating materials, such as silicon dioxide, silicon nitride, etc.
Openings are made through these protective layers to the silicon body both to provide impurity regions within the body as well as to allow conductive layers on top of the body to make contact to the impurity regions. In most instances it is important that the etchant be selective, i.e., it exhibits the property of attacking one of the protective layers without substantially attacking the silicon or the other protective layer. For example, dilute hydrofluoric acid buffered with ammonium fluoride has been used to etch silicon dioxide because it does not substantially attack silicon nitride or silicon. Similarly, hot phosphoric acid will attack silicon nitride while not attacking silicon dioxide, silicon or common photoresist layers.
I have found, however, that the standard buffered HF solution will attack N+ or N-type silicon during semiconductor processing. This is particularly true when the etching solution is in contact simultaneously with exposed highly doped silicon and platinum silicide. The cause is apparently an electrochemical reaction between the silicon and the platinum silicide, with the reaction connection being completed when the semiconductor is dipped into the standard buffered HF solution. This tends to dissolve the silicon, especially N+ silicon.
As an example, consider the fabrication of integrated TTL circuit chips in which PtSi is used both for the ohmic contacts, as well as high-barrier height Schottky barrier diode (SBD) contacts. This is one of the most common integrated circuit structures in the industry, and the fabrication process is well known. After the PtSi is formed in the contact regions, the excess Pt is removed by aqua regia etchant. The only protection for the PtSi is a thin and porous layer, around 30 A, of SiO.sub.2. Because the SiO.sub.2 is thin and porous, the aqua regia also may attack localized regions of the PtSi, thereby exposing the N+ or N type silicon in contact regions exposed beneath the PtSi. This, in itself, is not a major problem. However, the next step of standard fabrication process is the removal of the thin SiO.sub.2 layer from atop the PtSi using standard buffered HF solution. I have found that the buffered HF attacks the exposed N+ or N type silicon, most likely due to the aforesaid electrochemical reaction between the silicon and the PtSi. This expands the extent and depth of the silicon removal.
The next step in the TTL process is the deposition of a barrier metal such as Cr, Mo, Ti, W or alloys thereof which act as a barrier between the aluminum to be deposited as the interconnection metallurgy and the underlying PtSi and silicon. All of these barrier metals have a significantly lower forward voltage characteristic (Schottky barrier height) than PtSi, and any direct contact between the barrier metal and the N type silicon causes the voltage characteristic to shift, thereby rendering the circuit inoperative.
With regard to the N+ silicon contact regions, the extent of electrochemical dissolution is even worse than it is for N-silicon. The dissolution has caused deep alloying spikes which extend completely through the contact regions during subsequent high temperature processing.